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Renesas Electronics /R7FA2E2A7 /I3C /SCSTLCTL

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Interpret as SCSTLCTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STLCYC0 (0)AAPE 0 (0)TRAPE 0 (0)PARPE 0 (0)ACKPE

TRAPE=0, PARPE=0, AAPE=0, ACKPE=0

Description

SCL Stalling Control Register

Fields

STLCYC

Stalling Cycle
AAPE

Assigned Address Phase Enable

0 (0): Does not stall the SCL clock during the address assignment phase.

1 (1): Stall the SCL clock during address assignment phase.
TRAPE

Transition Phase Enable

0 (0): Does not stall the SCL clock during the transition bit in read transfer.

1 (1): Stall the SCL clock during the transition bit in read transfer.
PARPE

Parity Phase Enable

0 (0): Does not stall the SCL clock during the parity bit period.

1 (1): Stall the SCL clock during the parity bit period.
ACKPE

ACK phase Enable

0 (0): Does not stall the SCL clock during the ACK/NACK phase.

1 (1): Stall the SCL clock during the ACK/NACK phase.

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data